Canonical Forms

The functionality of any logic circuit can be expressed in one of two alternative and equivalent canonical forms. These canonical forms consist of a Boolean algebraic expression. They are generally developed from a truth table. They are

The construction of these forms is best illustrated by the examples below.


The Minterm Form

Consider the truth table below for the output Y from a combinatorial logic circuit comprising three inputs, A, B and C

ABCY
1111
1100
1010
1001
0110
0100
0010
0000

The first canonical form is developed from the output 1's in the truth table. As can be seen, Y is only 1 for the 1st and 4th rows of the truth table. Therefore the minterm (AND function) expressions for these two rows are formed and OR-ed together to give the minterm form for the circuit as

The corresponding circuit would be implemented with AND-OR logic i.e. with the outputs from one or more AND gates being OR-ed together to give the final output.


The Maxterm Form

Consider the truth table below for the output Y from a combinatorial logic circuit comprising three inputs, A, B and C

ABCY
1110
1101
1011
1000
0111
0101
0011
0001

The second canonical form is developed from the output 0's in the truth table. As can be seen, Y is only 0 for the 1st and 4th rows of the truth table. Developing the maxterm expression here is slightly more complicated and there are two approaches.

In the first approach we first develop the minterm expression for the output 0's (not 1's) in the truth table. For the truth table above this will be given by

Then it is necessary to apply the rules of Boolean algebra for converting minterm expressions to maxterm expressions as is described in the Boolean Algebra summary. This leads to the final maxterm form for this truth table of

The second approach allows the maxterm form to be derived directly from the output 0's in the truth table using the following rules.

In the case of the truth table above it is possible to go directly to the final maxterm form using this approach.

The corresponding circuit would be implemented with OR-AND logic i.e. with the outputs from one or more OR gates being AND-ed together to give the final output.


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