The JK flip-flop is an SRFF with some additional gating logic on the inputs which serve to overcome the SR=11 prohibited state in the SRFF. A simple JKFF is illustrated below
The SR=11 is not allowed in this configuration because both
and 
are fed back, one into each of
the AND gates. Since each AND gate requires all inputs to be 1 to give
an output of 1 then clearly it is impossible for both of these AND gates
to be 1 at the same time and so S and R cannot both be 1.
It should be noted that the circuit above is just one implementation of a JKFF. Another can be formed using the NAND gate version of the SRFF as illustrated in the lower circuit in the section Design of the SR flip-flop. In this case, since the SR inputs are complemented i.e. driven by 0 instead of 1, then the input gating logic would require NAND gates in place of the AND gates in the circuit above. In this case the full circuit, including the two asynchronous inputs for PRESET and CLEAR appears as below
A truth table can be developed for the output Q at time t (before a clock
pulse) and at time t+1 (after a clock pulse), this is given below (clearly,
the output is just the complement of Q).
| J | K | Qt | Qt+1 |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
The final two lines in the truth table represent oscillation between the two states on each rising CLK pulse. As was the case with the Delay flip-flop this results in division by two of the incoming CLK pulse as long as the clock pulse is short, otherwise oscillation may occur. This behaviour can be summarised as follows
takes the value of J on CLK pulse takes the value of K on CLK pulse