Selected Publications - Dr Mohammed Benaissa
Journal Papers
W Chelton and M Benaissa
Concurrent Error Detection in GF(2m) Multiplication and Its Application in ECC
IET Proceedings CDS, June 2008, pp.289-297
W Chelton and M Benaissa
Fast Elliptic Curve Cryptography on FPGA
IEEE Transactions on VLSI systems
Volume 16, Issue 2, Feb. 2008 Page(s):198 - 205
R.A. Patel, M. Benaissa and S. Boussakta
Novel Class of Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
IEEE Transactions on Computers
vol. 56, no. 11, Nov., 2007
R.A. Patel, M. Benaissa, S. Boussakta and N. Powell
Novel Power-Delay-Area efficient architectures for Generic Modular Addition
IEEE Transactions on Circuits and Systems I (TCASI)
vol.54, no.6, June 2007, pp.1279-1291
R.A. Patel, M. Benaissa and S. Boussakta
A New Class of Modular Adder for RNS
IEEE Transactions on Computers
vol. 56, no. 4, pp. 572-576, Apr., 2007
M. Benaissa and Y. Zhu
Reconfigurable Hardware Architectures for Sequential and Hybrid Decoding
IEEE transactions on Circuits and Systems (TCASI)
Vol.54, Issue 3, pp.555-565, March 2007
T. Good and M. Benaissa
Pipelined AES on FPGA with support for feedback modes
IET proceedings, Information Security
March 2007 , Volume 1, Issue 1, p. 1-10
R.A. Patel, M. Benaissa and S. Boussakta
An efficient New Approach for modulo 2n-1 addition in RNS
IEE Proceedings - Computers and Digital Techniques
November 2006 - Volume 153, Issue 6, p. 399-405
W. Chelton and M. Benaissa
Towards Secure Hardware for Elliptic Curve Cryptography
The Mediterranean Journal of Computers and Networks (MEDJCN), special issue on Advances in Biometrics,: Theory, Security and Applications
Volume 2, No. 4, October 2006, pp. 144 -150
M. Benaissa and W.M. Lim
Flexible GF(2m) Arithmetic Architectures for Subword Parallel Processing ASIPs
IEE proceedings CDT
Volume 153, Issue 5 , p. 291-301, September 2006
T. Good and M. Benaissa
Very small FPGA Application Specific Instruction Processor for AES
IEEE Transactions on Circuits and Systems I (TCASI)
Volume 53, Issue 7, July 2006 Page(s):1477 - 1486
M. Benaissa and W.M. Lim
Design of Flexible GF(2m) Elliptic Curve Processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume 14, Issue 6, June 2006 Page(s):659 - 662
T. Good and M. Benaissa
AES from the fastest to the smallest
Lecture Notes in Computer Science (LNCS 3659), Cryptographic Hardware and Embedded Systems-CHES 2005
pp. 427 – 440, Springer-Verlag, 2005
A. Patel, M. Benaissa, S. Boussakta and N. Powell
Power-Delay-Area efficient modulo 2n+1 adder architecture for RNS
Electronics Letters
41(5), 3 March 2005, pp.231-233
A.Mahran and M. Benaissa
Iterative Decoding with a Hamming Threshold for Block Turbo Codes Adaptive
IEEE Communications Letters
September 2004, Vol.8, No.9
A.Mahran and M. Benaissa
Adaptive Combined Chase-GMD Algorithms for Block Codes
IEEE Communications Letters
April 2004, Vol.8, No.4
M. Benaissa and Y. Zhu
A novel high speed configurable Viterbi decoder for broadband access
EURASIP Journal on Applied Signal Processing (Special Issue)
Vol.2003,No.13, pp.1317-1327, Dec.2003
A.Mahran and M. Benaissa
Adaptive Chase algorithm for block turbo codes
IEE Electronics Letters
39(7), April 2003, pp.617-619
C.J.A. Levita, M. Benaissa and I.J. Wassell
An Adaptable Viterbi Detector for a Decomposed CPM Model over Rings of Integers
IEE Proceedings Communication
Vol.147, No.3, June 2000, pp1-7
C.J.A. Levita, I.J. Wassell and M. Benaissa
Coded and uncoded CPM schemes over rings of integers for AWGN and Rayleigh fading channels
Electronics Letters
vol.35, No.9, 29th April 1999, pp. 696-698
R. Furness, M. Benaissa and S.T.J. Fenn
GF(2m) multiplication over the triangular basis for the design of Reed-Solomon codes
IEE Proc. Computers and Digital Techniques
Vol.145, No.6, Nov. 1998, pp.437-443
S. Smith, D. Taylor and M. Benaissa
Design automation of Reed-Solomon codecs using VHDL
The Microlectronics Journal
29, pp.977-982. 1998.
S.T.J. Fenn, M. Gossel, M. Benaissa and D. Taylor
On-line error detection for Bit-serial multiplication in GF(2m)
Journal of Electronic Testing, Theory and Applications
13, pp.29-40, 1998
R. Furness, M. Benaissa and S.T.J. Fenn
Finite-field Division based on the recursive division algorithm and composite fields
Electronics Letters
vol.34, No.8, 3rd September 1998, pp.1730-1731
S.T.J. Fenn, M.G. Parker, M. Benaissa and D. Taylor
Bit-serial multiplication in GF(2m) using irreducible all one polynomials
IEE Proc. Computers and Digital Techniques
Vol. 144, No. 6, Nov. 1997, pp. 391-393
M.G. Parker and M.Benaissa
Modular arithmetic using low-order redundant bases
IEEE Transactions on Computers
Vol.46, No.5, May 97, pp.611-616
S.T.J. Fenn, M. Benaissa and D. Taylor
Dual basis systolic multipliers for GF(2m)
IEE Proc. Computers and Digital Techniques
Vol.144, No.1, Jan. 97, pp.43-46
S.T.J. Fenn, M. Benaissa and D. Taylor
Fast normal basis inversion in GF(2m)
Electronic Letters
15 August 1996, Vol. 32, No. 17, pp. 1566-1567
S.T.J. Fenn, D. Taylor and M. Benaissa
Finite field inversion over the dual basis
IEEE Transactions on VLSI
4, March 1996, pp. 134-137
S.T.J. Fenn, M. Benaissa and D. Taylor
GF(2m) multiplication and division over the dual basis
IEEE Trans. Computers
54, March 1996, pp. 319-327
S.T.J. Fenn, M. Benaissa and D. Taylor
Decoding double error-correcting Reed-Solomon codes
IEE Proc. Comms
Vol. 142 No. 6, Dec. 1995, pp. 345-348
M.G. Parker and M. Benaissa
GF(pm) Multiplication using Polynomial Residue Number Systems
IEEE Trans CAS-II
vol. 42, No.11, Nov. 1995, pp. 718-721
S.T.J. Fenn, M. Benaissa and D. Taylor
Bit-serial Berlekamp-like multipliers for GF(2m)
Electronic Letters
26 Oct., 1995, 31, pp. 1893-1894
M.G. Parker and M. Benaissa
Unusual Length NTTs using recursive Rader's Algorithm
IEE Proc. Vision Image and Signal Processing
vol. 142, Feb. 1995, pp. 31-34
S.T.J. Fenn, D. Taylor and M. Benaissa
The design of Reed-Solomon codecs over the dual basis
Microelectronics Journal
26, 1995, pp. 383-391
S.T.J. Fenn, D. Taylor and M. Benaissa
A dual basis bit-serial systolic multiplier for GF(2m)
Integration: The VLSI Journal
18, 1995, pp. 139-149
M.G. Parker and M. Benaissa
VLSI structures for modular multiplication using basis conversion
IEE Proc. Computers and Digital Techniques
vol. 141, Nov. 1994, pp. 381-390
S.T.J. Fenn, M. Benaissa and D. Taylor
Improved algorithm for division over GF(2m)
Electronic Letters
Vol. 29, 4 March, 1993, pp. 469-470
M. Benaissa, S.S. Dlay and A.G.J Holt
VLSI implementation issues for the 2-D Fermat number transform
Journal of Signal Processing
vol 23 (3) 1991 pp 257-272
M. Benaissa, S.S. Dlay and A.G.J Holt
CMOS VLSI design of a high-speed Fermat nuber transform based convolver/correlator using 3-input adders
IEE proceedings
part G, vol 138 (2) April 1991, pp182-190
M. Benaissa, A. Pajayakrit, S.S. Dlay and A.G.J Holt
VLSI design for diminished-1 multiplication of integers modulo a Fermat number
IEE proceedings
vol. 135, pt. E, no. 3, May 1988 pp.161-164
M. Benaissa, A. Bouridane, S.S. Dlay and A.G.J Holt
A diminished-1 multiplier for a fast convolver/correlator using the Fermat number transform
IEE proceedings
vol. 135, pt. G, no.5 Oct. 1988, pp187-193
Refereed conferences
J Chu and M Benaissa
PRNS GF(2m)multiplier for ECC
accepted APCCAS 2008
M N Hassan, M Benaissa
Low area scalable Montgomery inversion over GF(2m)
accepted APCCAS 2008
M N Hassan, M Benaissa
Low area scalable Montgomery inversion over GF(2m)
Secrypt 2008, Porto, July 2008
T. Good and M. Benaissa
Price to provide security and privacy
SECRYPT 2008, Porto, July 2008
T. Good and M. Benaissa
Hardware performance of eStream phase-III stream cipher candidates
SASC2008, Lausanne, Feb 2008
T. Good and M. Benaissa
Hardware Results for Selected Stream Cipher
Proceedings of SASC2007
W. Chelton and M. Benaissa
Design Space Exploration of Division over GF(2m) on FPGA: A Digit-Serial Approach
proceedings IEEE ICECS 2006
Nice, France
A. Mahran and M. Benaissa
Parameters Selection of Block Turbo Codes using Genetic Algorithms
proceedings International Computer Engineering Conference
Engineering the Information Society (ICENCO'2006)
W. Chelton and M. Benaissa
High-Speed Pipelined ECC Processor on FPGA
Proceedings IEEE SIPS 2006
Banff, Canada
W. Chelton and M. Benaissa
Limiting Flexibility in Multiplication over GF(2m): A Design Methodology
Proceedings IEEE SIPS 2006
Banff, Canada
T. Good and M. Benaissa
AES as a stream cipher on a small FPGA
proceedings of IEEE ISCAS 2006
pp.629-533, Kos, Greece
T. Good, W. Chelton and M. Benaissa
Review of stream cipher candidates from a low resource hardware
proceedings of SASC 2006
T. Good and M. Benaissa
AES from the fastest to the smallest
CHES 2005 Edinburgh, Scotland
LNCS 3659, pp. 427 – 440, Springer-Verlag, 2005
R. Patel, M. Benaissa, N. Powell and S. Boussakta
ELMMA: A New Low-Power High-Speed Adder for RNS
Proceedings of IEEE SIPS 2004
Oct.2004, Austin, USA
W. Chelton and M. Benaissa
A Scalable GF(2m) Arithmetic Unit for Application in an ECC Processor
Proceedings of IEEE SIPS2004
Oct.2004, Austin, USA
A. Mahran and M. Benaissa
Adaptive Reliability Calculation for Block Turbo Codes
Proc. 58th IEEE Vehicular Technology Conference
VTC-Fall’03, Florida, USA, 6-9 Oct. 2003
Y. Zhu, M. Benaissa and W.M. Lim
A novel hybrid coding scheme
Proc. 58th IEEE Vehicular Technology Conf
VTC-Fall’03, Orlando, Florida, USA, 6-9 October 2003
W.M. Lim and M. Benaissa
Design Space Exploration of a Hardware-Software Co-designed GF(2m) Galois Field Processor for Forward Error Correction and Cryptography
Proc. CODE-ISSS 2003
Newport Beach, California, USA, 1-3 October 2003, pp.53-58
M. Benaissa and W.M. Lim
Online reconfigurable Hardware Implementations for Forward Error Correction and Cryptography: A primitive-based domain approach
Proc. IEE Colloquium on DSP Enabled Radio
Livingston, Scotland, 22-23 September 2003
A. Mahran and M. Benaissa
Iterative Decoding of Product Codes via Adaptive Application of the Combined Chase-2 and GMD Decoding Algorithm
Proc. 3rd International Symposium in Turbo Codes and related Topics
Brest, France. Sep. 2003, 367-370
W.M. Lim and M. Benaissa
Subword Parallel GF(2m) ALU: An Implementation for a Cryptographic Processor
Proc.2003 IEEE Workshop on Signal Processing Systems (SIPS’03)
27-29 August 2003, Seoul, South Korea, pp.63-68
A. Mahran and M. Benaissa
Efficient Turbo Product Codes for Burst and Random Errors corrections
Proc. 7th International Symposium on Communication Theory and Applications, ISCTA’03
Ambleside, UK, July 2003, pp. 259-263
Y. Zhu and M. Benaissa
A reconfigurable Fano Based sequential decoder
Proc. 7th International Symposium on Communication Theory and Applications, ISCTA’03
Ambleside, UK, July 2003, pp. 76-80
W.M. Lim and M. Benaissa
A Generic SISD/SIMD GF(2m) Galois Field Processor for Forward Error Correction and Cryptography
Proc. 7th International Symposium on Communication Theory and Applications, ISCTA’03
Ambleside, UK, July 2003, pp. 147-152
Y. Zhu and M. Benaissa
Reconfigurable Viterbi decoding using a new ACS pipelining technique
proceedings of ASAP’2003, 14th IEEE International Conference on Application-specific Systems, Architectures and Processors
The Hague, The Netherlands, 24-26 June 2003, pp. 348-357
Y. Zhu and M. Benaissa
A novel ACS scheme for area-efficient Viterbi decoders
proceedings of ISCAS’2003, IEEE International Symposium on Circuits and Systems
Bangkok, Thailand, 25-28 May 2003, vol. 2, pp. 264-267
A. Mahran and M. Benaissa
Adaptive Application of the Chase Algorithm on Reed-Solomon Product Codes
Proc. 5th European Personal Communication Conference
Glasgow, UK, Apr. 2003, pp. 343-347
A. Mahmudi, M. Benaissa and P. Sweeney
The Implementation of Generalised Minimum Distance Decoding for Reed Solomon Codes
Proceeding of ISCAS 2000, May 2000
Geneva, Vol.IV, pp. 53-56
A. Mahmudi, M. Benaissa and P. Sweeney
On the Implementation of Soft-Decision-Decoding for RS codes
Proceedings of PIMRC2000
London, Vol.1, pp.170-174
R. Furness, M. Benaissa and S.T.J. Fenn
Circuit architectures for semi-bit-serial and programmable arithmetic in finite fields
Proceedings of the IEEE conference on Electronics, Circuits and Systems
September 98, Lisbon
E. Jamro, S.T.J. Fenn, D. Taylor and M. Benaissa
Hardware efficient multiplication in Berlekamp-Massey algorithm circuits
CDSP’98
Sheffield, April 1998, pp. 60-63
R. Furness, M. Benaissa and S.T.J. Fenn
Semi-bit serial architectures over finite fields for the design of RS codes
CDSP’98
Sheffield, April 1998, pp. 125-128
R. Furness, M. Benaissa and S.T.J. Fenn
Generalised triangular basis multipliers for the design of Reed-Solomon codecs
IEEE Workshop on Signal Processing Systems
Leicester, 3-5 Nov., 1997, pp.202-211
R. Furness, S.T.J. Fenn and M. Benaissa
Multiplication using the triangular basis representation over GF(2m)
GLOBECOM’96
Nov. 18-22, London, 1996
S.T.J. Fenn, M. Benaissa, D. Taylor and J. Luty
Programmable bit-serial Reed-Solomon encoders
EUSIPCO’96
Trieste 10-13 September 1996, pp. 1299-1302
S.T.J. Fenn, M. Benaissa and D. Taylor
Bit-serial dual basis systolic multipliers for GF(2m)
ISCAS'95
Seattle, May 1995, pp. 3.200- 3.2003
S.T.J. Fenn, M. Benaissa and D. Taylor
Solving simultaneous linear equations over GF(p)
EUSIPCO'94
Edinburgh, September 1994, pp. 1879-1882
S.T.J. Fenn, M. Benaissa and D. Taylor
Fast Chien search for BCH and RS decoders
Communication Network Symposium
Manchester, 11-12 July 1994, pp. 34-37
M.G. Parker and M. Benaissa
Fault-tolerant linear convolution using RNS
Proc. ISCAS94
IEEE, London, 30 May - 2 June 1994, pp. 441-444
S.T.J. Fenn, D. Taylor and M. Benaissa
A dual basis systolic divider for GF(2m)
ISCAS'94
London 30 May - 2 June 1994, pp. 307-310
S.T.J. Fenn, C.R. Johnson, M. Benaissa and D. Taylor
Fast prototyping complex digital systems: A case study using Reed-Solomon codecs
IEE Colloquium on Fast Prototyping of IC Design
2 June London, 1994, 7/1-7/6
S. Smith, D. Taylor and M. Benaissa
Generation of generic descriptions of (n,k) RS codecs using VHDL
CEEDA'94
Bournemouth, 7-8 April 1994
S.T.J. Fenn, M. Benaissa and D. Taylor
Rapid prototyping of Reed-Solomon codecs using Field Programmable Gate Arrays
CEEDA'94
Bournemouth, 7-8 April 1994, pp. 309-312
M.G. Parker and M.Benaissa
Using Redundant Number Representations for Efficient VLSI Implementation of Modular Arithmetic
Proc of IEE Coll. on "Synthesis and Optimisation of Logic Systems"
(E3,E10), Savoy Place, London, 14th Mar, 1994, Digest No: 1994/066
S.T.J. Fenn, D. Taylor and M. Benaissa
Decoding double-error correcting Reed-Solomon codes
5th Bangor Communications Symposium
June 2-3, 1993, pp. 12-15
M.G. Parker and M. Benaissa
Bit-serial VLSI architecture for the implementation of maximum length NTTS using mixed-basis representations
Proc. of ICASSP93
Vol.1, pp.341-344, April 93
S. Smith, M. Benaissa and D. Taylor
High-level Synthesis of an (n,k) Reed-Solomon encoder using VHDL
VHDL (Very High Speed Integrated Circuits Hardware Description Language) - Applications and CAE Advances
IEE Colloquium on (Digest No.1993/076), 6 Apr 1993 Page(s):1/1 - 1/4
M.G. Parker and M. Benaissa
A Bit-Serial, VLSI Implementation of a 60-Point NTT Using Binary and Ternary Bases
Digest of Int. Symp. on DSP for Communication Systems
Univ. of Warwick 7-9th Sept 1992
M. Benaissa
VLSI Implementation issues of 1-D and 2-D FNT-based systems and applications
Proc. of ICDSPAT
Berlin 1991, pp.262-274
Book Chapters
M Benaissa and T Good
Hardware Performance” in The eSTREAM Finalists
LNCS state-of-the-art series, M. Robshaw, Ed.
vol. 4986. Springer-Verlag, 2008